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| rev. 2.0 november 2006 1/117 ST7260 low speed usb 8-bit mcu family with up to 8k flash/rom and serial communication interface (sci) memories ? 4 or 8 kbytes program memory: high density flash (hdflash), fastrom or rom with re- adout and write protection ? in-application programming (iap) and in-cir- cuit programming (icp) ? 384 bytes ram memory (128-byte stack) clock, reset and supply management ? run, wait, slow and halt cpu modes ? 12 or 24 mhz oscillator ? ram retention mode ? optional low voltage detector (lvd) usb (universal serial bus) interface ? dma for low speed a pplications compliant with usb 1.5 mbs (version 2.0) and hid spec- ifications (version 1.0) ? integrated 3.3 v voltage regulator and trans- ceivers ? supports usb dfu class specification ? suspend and resume operations ? 3 endpoints with programmable in/out config- uration up to 19 i/o ports ? up to 8 high sink i/os (10 ma at 1.3 v) ? 2 very high sink true open drain i/os (25 ma at 1.5 v) ? up to 8 lines individually programmable as in- terrupt inputs 2 timers ? programmable watchdog ? 16-bit timer with 2 input captures, 2 output compares, pwm output and clock input 1 communication interface ? asynchronous serial communications inter- face instruction set ? 63 basic instructions ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction ? true bit manipulation development tools ? versatile development tools (under win- dows) including assemb ler, linker, c-compil- er, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers, hid and dfu software layers table 1. device summary so24 qfn40 (6x6) features ST7260k2 ST7260k1 ST7260e2 ST7260e1 program memory -bytes (flash or rom) 8 k 4 k 8 k 4 k ram (stack) - bytes 384 (128) standard peripherals watchdog ti mer, 16-bit timer, usb other peripherals sci operating supply 4.0 v to 5.5 v cpu frequency 8 mhz (with 24 mhz oscillator) or 4 mhz (with 12 mhz oscillator) operating temperature 0 c to +70 c packages qfn40 (6x6) qfn40 (6x6) so24 1
table of contents 117 2/117 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.3 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table of contents 3/117 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.10communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 101 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 14.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 15 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 107 15.1 option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 15.2 device ordering inform ation and transfer of customer code . . . . . 108 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 16 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.1 pa2 limitation with ocmp1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.2 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.3 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.4 usb behavior with lvd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ST7260 4/117 1 introduction the ST7260 microcontrollers form a sub-family of the st7 mcus dedicated to usb applications. the devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. they operate at a 24 mhz or 12 mhz oscillator fre- quency. under software control, the ST7260 mcus may be placed in either wait or halt modes, thus reducing power consumption. the enhanced instruction set and addressing modes afford real programming potential. in addition to standard 8- bit data management, the ST7260 mcus feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the devices in- clude an st7 core, up to 8kbytes of program memory, up to 384 bytes of ram, 19 i/o lines and the following on-chip peripherals: ? usb low speed interface with 3 endpoints with programmable in/out configuration using the dma architecture with embedded 3.3v voltage regulator and transceivers (no external compo- nents are needed). ? industry standard asynchronous sci serial inter- face ? watchdog ? 16-bit timer featuring an external clock input, 2 input captures, 2 output compares with pulse generator capabilities ? low voltage reset (lvd) ensuring proper power- on or power-off of the device the st72f60 devices ar e flash versions. they support programming in iap mode (in-application programming) via the on-chip usb interface. figure 1. general block diagram 8-bit core alu address and data bus oscin oscout reset port b 16-bit timer port a port c pb[7:0] (8 bits) pc[2:0] (3 bits) oscillator internal clock control ram (384 bytes) pa[7:0] (8 bits) v ss v dd power supply sci program (8k bytes) memory (uart) usb sie osc/3 lvd watchdog v ssa v dda v pp /test usb dma usbdp usbdm usbvcc osc/4 or osc/2 for usb 1) 1) 12 or 24 mhz oscin frequency required to generate 6 mhz usb clock. ST7260 5/117 2 pin description figure 2. 40-lead qfn package pinout 4 3 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 2 1 35 36 13 14 v dda v dd oscout oscin vss usboe/pc2 v ssa usbdp usbdm usbv cc nc it8/pb7 (10ma) it7/pb6 (10ma) tdo/pc1 rdi/pc0 rese t nc it6/pb5 (10ma) v pp /test pa7/ocmp2/it4 pb0 (10ma) pb1 (10ma) pb2 (10ma) pb3 (10ma) pb4 (10ma) /it5 pa3/extclk pa4/icap1/it1 pa5/icap2/it2 pa6/ocmp1/it3 nc nc nc nc nc nc pa2 (25ma) /iccclk pa1 (25ma) /iccdata nc nc pa0/mco note: nc=do not connect ST7260 6/117 figure 3. 24-pin so package pinout 14 13 11 12 15 16 17 18 pa2 (25ma) /iccclk pa1 (25ma) /iccdata pa0/mco v ssa pa7/ocmp2/it4 pa5/icap2/it2 pa4/icap1/it1 1 2 3 4 5 6 7 8 9 10 v dd rdi/pc0 tdo/pc1 v ss pa3/extclk it7/pb6 (10ma) 19 20 v pp /test pb3 (10ma) pb2 (10ma) usbdp reset / oscout usboe/pb1 (10ma) pb0 (10ma) oscin 21 22 23 24 usbdm usbvcc ST7260 7/117 pin description (cont?d) reset (see note 1): bidirectional. this active low signal forces the initialization of the mcu. this event is the top priority non maskable interrupt. this pin is switched low when the watchdog is trig- gered or the v dd is low. it can be used to reset ex- ternal peripherals. oscin/oscout: input/output oscillator pin. these pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. v dd /v ss (see note 2): main power supply and ground voltages. v dda /v ssa (see note 2): power supply and ground voltages for analog peripherals. alternate functions : several pins of the i/o ports assume software programmable alternate func- tions as shown in the pin description. note 1 : adding two 100 nf decoupling capacitors on the reset pin (respectively connected to v dd and v ss ) will significantly improve product electro- magnetic susceptibility performance. note 2 : to enhance the reliab ility of operation, it is recommended that v dda and v dd be connected to- gether on the application board. this also applies to v ssa and v ss . note 3: the usboe alternate function is mapped on port c2 in qfn40 devices. in so24 devices it is mapped on port b1. note 4: the timer ocmp1 alternate function is mapped on port a6 in qfn40 pin devices. in so24 devices it is not available. legend / abbreviations for table 2 , table 3 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3 v dd / 0.7 v dd with input trigger output level: 10 ma = 10 ma high sink (fn n-buffer only) 25 ma = 25 ma very high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, int = interrupt ? output: od = open drain, pp = push-pull, t = true open drain the reset configuration of each pin is shown in bold. this configuration is kept as long as the de- vice is under reset state. ST7260 8/117 table 2. device pin description (qfn40) pin n pin name type level port / control main function (after reset) alternate function qfn40 input output input output float wpu int od pp 7v dd s power supply voltage (4v - 5.5v) 8 oscout o oscillator output 9 oscin i oscillator input 10 v ss s digital ground 11 pc2/usboe i/o c t x x port c2 usb output enable 12 pc1/tdo i/o c t x x port c1 sci transmit data output 13 pc0/rdi i/o c t x x port c0 sci receive data input 14 reset i/o x x reset 15 nc -- not connected 16 nc -- not connected 17 pb7/it8 i/o c t 10ma x xx port b7 18 pb6/it7 i/o c t 10ma x xx port b6 19 v pp /test s programming supply 20 pb5/it6 i/o c t 10ma x xx port b5 21 pb4/it5 i/o c t 10ma x xx port b4 22 pb3 i/o c t 10ma x x port b3 23 pb2 i/o c t 10ma x x port b2 24 pb1 i/o c t 10ma x x port b1 25 pb0 i/o c t 10ma x x port b0 26 pa7/ocmp2/it4 i/o c t x xx port a7 timer output compare 2 27 pa6/ocmp1/it3 i/o c t x xx port a6 timer output compare 1 28 pa5/icap2/it2 i/o c t x xx port a5 timer input capture 2 29 pa4/icap1/it1 i/o c t x xx port a4 timer input capture 1 30 pa3/extclk i/o c t x x port a3 timer external clock 31 pa2/iccclk i/o c t 25ma x t port a2 icc clock 32 nc -- do not connect 33 nc -- do not connect 34 nc -- do not connect 35 nc -- do not connect 36 nc -- do not connect 37 nc -- do not connect 38 nc -- do not connect ST7260 9/117 table 3. device pin description (so24) 39 nc -- do not connect 40 pa1/iccdata i/o c t 25ma x t port a1 icc data 1 pa0/mco i/o c t xx port a0 main clock output 2v ssa s analog ground 3 usbdp i/o usb bidirectional data (data +) 4 usbdm i/o usb bidirectional data (data -) 5 usbvcc o usb power supply 6v dda s analog supply voltage pin n pin name type level port / control main function (after reset) alternate function qfn40 input output input output float wpu int od pp pin n pin name type level port / control main function (after reset) alternate function so24 input output input output float wpu int od pp 1v dd s power supply voltage (4v - 5.5v) 2 oscout o oscillator output 3 oscin i oscillator input 4v ss s digital ground 5 pc1/tdo i/o c t x x port c1 sci transmit data output 6 pc0/rdi i/o c t x x port c0 sci receive data input 7 reset i/o x x reset 8 pb6/it7 i/o c t 10ma x xx port b6 9v pp /test s programming supply 10 pb3 i/o c t 10ma x x port b3 11 pb2 i/o c t 10ma x x port b2 12 pb1/usboe i/o c t 10ma x x port b1 usb output enable 13 pb0 i/o c t 10ma x x port b0 14 pa7/ocmp2/it4 i/o c t x xx port a7 timer output compare 2 15 pa5/icap2/it2 i/o c t x xx port a5 timer input capture 2 16 pa4/icap1/it1 i/o c t x xx port a4 timer input capture 1 17 pa3/extclk i/o c t x x port a3 timer external clock 18 pa2/iccclk i/o c t 25ma x t port a2 icc clock 19 pa1/iccdata i/o c t 25ma x t port a1 icc data ST7260 10/117 20 pa0/mco i/o c t xx port a0 main clock output 21 v ssa s analog ground 22 usbdp i/o usb bidirectional data (data +) 23 usbdm i/o usb bidirectional data (data -) 24 usbvcc o usb power supply pin n pin name type level port / control main function (after reset) alternate function so24 input output input output float wpu int od pp ST7260 11/117 3 register & memory map as shown in figure 4 , the mcu is capable of ad- dressing 8 kbytes of memories and i/o registers. the available memory locations consist of up to 384 bytes of ram including 64 bytes of register lo- cations, and up to 8k bytes of user program mem- ory in which the upper 32 bytes are reserved for in- terrupt vectors. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. important : memory locations noted ?re- served? must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 4. memory map table 4. interrupt vector map vector address description masked by remarks exit from halt mode ffe0h-ffedh ffeeh-ffefh fff0h-fff1h fff2h-fff3h fff4h-fff5h fff6h-fff7h fff8h-fff9h fffah-fffbh fffch-fffdh fffeh-ffffh reserved area usb interrupt vector sci interrupt vector reserved area timer interrupt vector it1 to it8 interrupt vector usb end suspend mode interrupt vector flash start programming interrupt vector trap (software) interrupt vector reset vector i- bit i- bit i- bit i- bit i- bit i- bit none none internal interrupt internal interrupt internal interrupt external interrupt external interrupts internal interrupt cpu interrupt no no no yes yes yes no yes 0000h ram program memory (4 / 8 kbytes) interrupt & reset vectors hw registers 0040h 003fh ffdfh ffe0h ffffh reserved stack (128 bytes) 0100h 017fh 01c0h 00ffh 0040h 0180h 01bfh short addressing ram (192 bytes) 16-bit addressing ram 8000h 7fffh (see table 5) (see table 4) (384 bytes) ffdfh f000h e000h 8 kbytes 4 kbytes 01bfh ST7260 12/117 table 5. hardware register memory map address block register label register name reset status remarks 0000h 0001h port a padr paddr port a data register port a data direction register 00h 00h r/w r/w 0002h 0003h port b pbdr pbddr port b data register port b data direction register 00h 00h r/w r/w 0004h 0005h port c pcdr pcddr port c data register port c data direction register 1111 x000b 1111 x000b r/w r/w 0006h to 0007h reserved (2 bytes) 0008h itc itifre interr upt register 00h r/w 0009h misc miscr miscellaneous register 00h r/w 000ah to 000bh reserved (2 bytes) 000ch wdg wdgcr watchdog control register 7fh r/w 000dh to 0010h reserved (4 bytes) 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh tim tcr2 tcr1 tcsr tic1hr tic1lr toc1hr toc1lr tchr tclr tachr taclr tic2hr tic2lr toc2hr toc2lr timer control register 2 timer control register 1 timer control/status register timer input capture high register 1 timer input capture low register 1 timer output compare high register 1 timer output compare low register 1 timer counter high register timer counter low register timer alternate counter high register timer alternate counter low register timer input capture high register 2 timer input capture low register 2 timer output compare high register 2 timer output compare low register 2 00h 00h 00h xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only r/w read only r/w read only read only r/w r/w 0020h 0021h 0022h 0023h 0024h sci scisr scidr scibrr scicr1 scicr2 sci status register sci data register sci baud rate register sci control register 1 sci control register 2 c0h xxh 00h x000 0000b 00h read only r/w r/w r/w r/w ST7260 13/117 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h usb usbpidr usbdmar usbidr usbistr usbimr usbctlr usbdaddr usbep0ra usbep0rb usbep1ra usbep1rb usbep2ra usbep2rb usb pid register usb dma address register usb interrupt/dma register usb interrupt status register usb interrupt mask register usb control register usb device address register usb endpoint 0 register a usb endpoint 0 register b usb endpoint 1 register a usb endpoint 1 register b usb endpoint 2 register a usb endpoint 2 register b x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0032h 0036h reserved (5 bytes) 0037h flash fcsr flash control /status register 00h r/w 0038h to 003fh reserved (8 bytes) address block register label register name reset status remarks ST7260 14/117 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a byte-by-byte ba- sis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features 3 flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. ? iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection register access securi ty system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 6 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 5 ). they are mapped in the upper part of the st7 addressing space so the reset and in- terrupt vectors are located in sector 0 (f000h- ffffh). table 6. sectors available in flash devices 4.3.1 read-out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. even if no protection can be considered as to- tally unbreakable, the feature provides a very high level of protection for a general purpose microcon- troller. in flash devices, this protection is removed by re- programming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. figure 5. memory map and sector address flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8 kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k ST7260 15/117 flash program memory (cont?d) 4.4 icc interface icc (in-circuit communication) needs a minimum of four and up to six pins to be connected to the programming tool (see figure 6 ). these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input/output serial data pin ? iccsel/v pp : programming voltage ? osc1(or oscin): main clock input for exter- nal source (optional) ?v dd : application board power supply (see fig- ure 6 , note 3) figure 6. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icc session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. when using a classical rc network with r > 1k or a reset man- agement ic with open drain output and pull-up resistor > 1k, no additional components are need- ed. in all cases the user must ensure that no exter- nal reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or os- cin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator ca pability need to have osc2 grounded in this case. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k ? v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4) ST7260 16/117 flash program memory (cont?d) 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circu it communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 6 ). for more details on the pin locations, refer to the device pinout de- scription. 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci or other type of serial interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation. 4.7 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.8 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. 70 00000000 ST7260 17/117 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 5.3 cpu registers the six cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 7. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value ST7260 18/117 cpu registers (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most signif icant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. 70 111hinzc ST7260 19/117 cpu registers (cont?d) stack pointer (sp) read/write reset value: 017fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 128 bytes deep, the 9 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 . ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five location s in the stack area. figure 8. stack manipulation example 15 8 00000001 70 0 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h ST7260 20/117 6 reset and clock management 6.1 reset the reset procedure is used to provide an orderly software start-up or to exit low power modes. three reset modes are provided: a low voltage (lvd) reset, a watchdog reset and an external re- set at the reset pin. a reset causes the reset vector to be fetched from addresses fffeh and ffffh in order to be loaded into the pc and with program execution starting from this point. an internal circuitry prov ides a 4096 cpu clock cy- cle delay from the time that the oscillator becomes active. 6.1.1 low voltage detector (lvd) low voltage reset circuitry generates a reset when v dd is: below v it+ when v dd is rising, below v it- when v dd is falling. during low voltage reset, the reset pin is held low, thus permitting the mcu to reset other devices. it is recommended to make sure that the v dd sup- ply voltage rises monotonously when the device is exiting from reset, to ensure the application func- tions properly. 6.1.2 watchdog reset when a watchdog reset occurs, the reset pin is pulled low permitting the mcu to reset other devic- es in the same way as the low voltage reset ( fig- ure 9 ). 6.1.3 external reset the external reset is an active low input signal ap- plied to the reset pin of the mcu. as shown in figure 12 , the reset signal must stay low for a minimum of one and a half cpu clock cycles. an internal schmitt trigger at the reset pin is pro- vided to improve noise immunity. figure 9. low voltage det ector functional diagram figure 10. low voltage reset signal output note : hysteresis (v it+ -v it- ) = v hys figure 11. temporization timing diagram after an internal reset low voltage v dd from watchdog reset reset internal detector reset reset v dd v it+ v it- v dd addresses $fffe temporization (4096 cpu clock cycles) v it+ ST7260 21/117 reset (cont?d) figure 12. reset timing diagram note: refer to electrical characteristics for values of t ddr , t oxov , v it+ , v it- and v hys v dd oscin f cpu ffff fffe pc reset watchdog reset t ddr t oxov 4096 cpu clock cycles delay ST7260 22/117 6.2 clock system 6.2.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (f cpu ) is de- rived from the external oscillator frequency (f osc ), which is divided by 3 (and by 2 or 4 for usb, de- pending on the external clock used). the internal clock is further divided by 2 by setting the sms bit in the miscellaneous register. using the osc24/12 bit in the option byte, a 12 mhz or a 24 mhz external clock can be used to provide an internal frequency of either 2, 4 or 8 mhz while maintaining a 6 mhz for the usb (refer to figure 15 ). the internal clock signal (f cpu ) is also routed to the on-chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal osc illator is designed to operate with an at-cut parallel resonant quartz or ceramic res- onator in the frequency range specified for f osc . the circuit shown in figure 14 is recommended when using a crystal, and table 7, "recommend- ed values for 24 mhz crystal resonator" lists the recommended capacitance. the crystal and asso- ciated components should be mounted as close as possible to the input pins in order to minimize out- put distortion and star t-up stabilisation time. table 7. recommended values for 24 mhz crystal resonator note: r smax is the equivalent seri al resistor of the crystal (see crystal specification). 6.2.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 13 . the t oxov specifications do not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see sec- tion 6.5 control timing). figure 13. external clock source connections figure 14. crystal/ ceramic resonator figure 15. clock block diagram r smax 20 ? 25 ? 70 ? c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m ? 1-10 m ? 1-10 m ? oscin oscout external clock nc oscin oscout c oscin c oscout r p %3 cpu and 8, 4 or 2 mhz 6 mhz (usb) 24 or peripherals) %2 1 0 %2 12 mhz crystal %2 0 1 osc24/12 sms %2 ST7260 23/117 7 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in table 8, "interrupt mapping" and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 16 . the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? the i bit of the cc register is set to prevent addi- tional interrupts. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 8, "interrupt mapping" for vector address- es). the interrupt service routine should finish with the iret instruction which caus es the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case several interrupts are simultaneously pending, a hardware priori ty defines which one will be serviced first (see table 8, "interrupt map- ping" ). non-maskable software interrupts this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced acco rding to the flowchart on figure 16 . interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specific men- tioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in table 8, "interrupt mapping" ). external interrupts the pins iti/pak and itj/pbk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge oc- curs on this pin. conversely, the itl/pan and itm/ pbn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. interrupt gene ration will occur if it is enabled with the itie bit (i=1 to 8) in the itrfre register and if the i bit of the ccr is reset. peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ? the i bit of the cc register is cleared. ? the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by one of the two following operations: ? writing ?0? to the corresponding bit in the status register. ? accessing the status register while the flag is set followed by a read or write of an associated reg- ister. notes : 1. the clearing sequence resets the internal latch. a pending inte rrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequence is executed. 2. all interrupts allow the processor to leave the wait low power mode. 3. exit from halt mode may only be triggered by an external interrupt on one of the iti ports (pa4-pa7 and pb4-pb7), an end suspend mode interrupt coming from usb peripheral, or a reset. ST7260 24/117 interrupts (cont?d) figure 16. interrupt processing flowchart table 8. interrupt mapping bit i set y n iret y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n n source block description register label priority order exit from halt vector address reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh flash flash start programming interrupt yes fffah-fffbh usb end suspend mode istr yes fff8h-fff9h 1 iti external interrupts itrfre fff6h-fff7h 2 timer timer peripheral interrupts timsr no fff4h-fff5h 3 reserved fff2h-fff3h 4 sci sci peripheral interrupts scisr fff0h-fff1h 5 usb usb peripheral interrupts istr ffeeh-ffefh ST7260 25/117 interrupts (cont?d) 7.1 interrupt register interrupts register (itrfre) address: 0008h ? read/write reset value: 0000 0000 (00h) bit 7:0 = itie (i=1 to 8) . interrupt enable control bits . if an itie bit is set, the corresponding interrupt is generated when ? a rising edge occurs on the pin pa4/it1 or pa5/ it2 or pb4/it5 or pb5/it6 or ? a falling edge occurs on the pin pa6/it3 or pa7/ it4 or pb6/it7 or pb7/it8 no interrupt is generated elsewhere. 70 it8e it7e it6e it5e it4e it3e it2e it1e ST7260 26/117 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the st7. after a reset, the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. 8.2 halt mode the mcu consumes the least amount of power in halt mode. the halt mode is entered by exe- cuting the halt instructio n. the internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the condi- tion code register is cleared. thus, all external in- terrupts (iti or usb end suspend mode) are al- lowed and if an interrupt occurs, the cpu clock be- comes active. the mcu can exit halt mode on reception of ei- ther an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, or a reset. the oscillator is th en turned on and a stabi- lization time is provided before releasing cpu op- eration. the stabilization time is 4096 cpu clock cycles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 17. halt mode flow chart n n external interrupt* reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y note: before servicing an in terrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped. ST7260 27/117 power saving modes (cont?d) 8.3 slow mode in slow mode, the oscilla tor frequency can be di- vided by 2 as selected by the sms bit in the mis- cellaneous register. the cpu and peripherals are clocked at this lower frequency. slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the avail- able supply voltage. 8.4 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0 to enable all interrupts. a ll other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 18 . related documentation an 980: st7 keypad decoding techniques, im- plementing wake-up on keystroke an1014: how to minimize the st7 power con- sumption an1605: using an active rc to wakeup the st7lite0 from power saving mode figure 18. wait mode flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 4096 cpu clock cycles delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped. ST7260 28/117 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: ? transfer of data through digital inputs and out- puts and for specific pins ? alternate signal input/output for the on-chip pe- ripherals ? external interrupt generation an i/o port consists of up to 8 pins. each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 9.2 functional description each port is associated to 2 main registers: ? data register (dr) ? data direction register (ddr) each i/o pin may be programmed using the corre- sponding register bits in ddr register: bit x corre- sponding to pin x of the port. the same corre- spondence is used for the dr register. table 9. i/o pin functions input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. note 1 : all the inputs are triggered by a schmitt trigger. note 2 : when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is con- figured as an output. interrupt function when an i/o is configured as an input with inter- rupt, an event on this i/o can generate an external interrupt request to the cpu. the interrupt sensi- tivity is given independently according to the de- scription mentioned in the itrfre interrupt regis- ter. each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as an interrupt source, this is logically ored. for this reason if one of the interrupt pins is tied low, the other ones are masked. output mode the pin is configured in output mode by setting the corresponding ddr register bit (see table 7). in this mode, writing ?0? or ?1? to the dr register applies this digital value to the i/o pin through the latch. therefore, the previously saved value is re- stored when the dr register is read. note : the interrupt function is disabled in this mode. digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin?s state is also digitally readable by addressing the dr register. notes : 1. input pull-up configuration can cause an unex- pected value at the input of the alternate peripher- al input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : the alternate function must not be acti- vated as long as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts. ddr mode 0 input 1 output ST7260 29/117 i/o ports (cont?d) 9.2.1 port a table 10. port a0, a3, a4, a5, a6, a7 description figure 19. pa0, pa3, pa4, pa 5, pa6, pa7 configuration port a i / o alternate function input 1 output signal condition pa0 with pull-up push-pull mco (mai n clock output) mco = 1 (miscr) pa3 with pull-up push-pull timer extclk cc1 =1 cc0 = 1 (timer cr2) pa4 with pull-up push-pull timer icap1 it1 schmitt triggered input it1e = 1 (itifre) pa5 with pull-up push-pull timer icap2 it2 schmitt triggered i nput it2e = 1 (itifre) pa6 2 with pull-up push-pull timer ocmp1 oc1e = 1 it3 schmitt triggered i nput it3e = 1 (itifre) pa7 with pull-up push-pull timer ocmp2 oc2e = 1 it4 schmitt triggered i nput it4e = 1 (itifre) 1 reset state 2 not available on so24 dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd diodes data bus ST7260 30/117 i/o ports (cont?d) table 11. pa1, pa2 description figure 20. pa1, pa2 configuration port a i / o alternate function input 1 output signal condition pa1 without pull-up very high current open drain pa2 without pull-up very high current open drain 1 reset state dr ddr latch latch dr sel ddr sel pa d alternate enable alternate enable alternate output n-buffer 1 0 1 0 cmos schmitt trigger v ss data bus ST7260 31/117 i/o ports (cont?d) 9.2.2 port b table 12. port b description port b i/o alternate function input 1 output signal condition pb0 without pull-up push-pull pb1 without pull-up push-pull usboe (usb output ena- ble) 2 usboe =1 (miscr) pb2 without pull-up push-pull pb3 without pull-up push-pull pb4 without pull-up push-pull it5 schmitt triggered input it4e = 1 (itifre) pb5 without pull-up push-pull it6 schmitt triggered input it5e = 1 (itifre) pb6 without pull-up push-pull it7 schmitt triggered input it6e = 1 (itifre) pb7 without pull-up push-pull it8 schmitt triggered input it7e = 1 (itifre) 1 reset state 2 on so24 only ST7260 32/117 figure 21. port b configuration dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable digital enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 v ss data bus v dd diodes ST7260 33/117 i/o ports (cont?d) 9.2.3 port c table 13. port c description figure 22. port c configuration port c i / o alternate function input 1 output signal condition pc0 with pull-up push-pull rdi (sci input) pc1 with pull-up push-pull tdo (sci output) sci enable pc2 2 with pull-up push-pull usboe (usb output ena- ble) usboe =1 (miscr) 1 reset state 2 not available on so24 dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd data bus diodes ST7260 34/117 i/o ports (cont?d) 9.2.4 register description data registers (pxdr) port a data register (padr): 0000h port b data register (pbdr): 0002h port c data register (pcdr): 0004h read/write reset value port a: 0000 0000 (00h) reset value port b: 0000 0000 (00h) reset value port c: 1111 x000 (fxh) note: for port c, unused bits (7-3) are not acces- sible. bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital val- ue applied to the i/o pin (pin configured as input). note: when using open-drain i/os in output con- figuration, the value read in dr is the digital value applied to the i/opin. data direction register (pxddr) port a data direction register (paddr): 0001h port b data direction register (pbddr): 0003h port c data direction register (pcddr): 0005h read/write reset value port a: 0000 0000 (00h) reset value port b: 0000 0000 (00h) reset value port c: 1111 x000 (fxh) note: for port c, unused bits (7-3) are not acces- sible bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode table 14. i/o ports register map related documentation an 970: spi communication between st7 and eeprom an1048: software lcd driver 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 address (hex.) register label 76543210 00 padr msb lsb 01 paddr msb lsb 02 pbdr msb lsb 03 pbddr msb lsb 04 pcdr msb lsb 05 pcddr msb lsb 06 reserved 07 reserved ST7260 35/117 10 miscellaneous register address: 0009h ? read/write reset value: 0000 0000 (00h) bit 7:3 = reserved bit 2 = sms slow mode select . this bit is set by softwa re and only cleared by hard- ware after a reset. if this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to fig- ure 15 on page 22 ). the sms bit has no effect on the usb frequency. 0: divide-by-2 disabled and cpu clock frequency is standard 1: divide-by-2 enabled and cpu clock frequency is halved. bit 1 = usboe usb enable. if this bit is set, the port pc2 (pb1 on so24) out- puts the usb output enable signal (at ?1? when the st7 usb is transmitting data). unused bits 7-4 are set. bit 0 = mco main clock out selection this bit enables the mco alternate function on the pa0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) 70 - - - - - sms usboe mco ST7260 36/117 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter?s contents before the t6 bit be- comes cleared. 11.1.2 main features programmable free-running counter (64 increments of 49,152 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte. 11.1.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 49,152 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low th e reset pin for typically 30s. the application program mu st write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. this downcounter is free- running: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 15, ". watchdog timing (fcpu = 8 mhz)" ): ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an imme- diate reset ? the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. figure 23. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 49152 t1 t2 t3 t4 t5 ST7260 37/117 watchdog timer (cont?d) table 15. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 11.1.4 software watchdog option if software watchdog is selected by option byte, the watchdog is disabled following a reset. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 11.1.5 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. 11.1.6 low power modes wait instruction no effect on watchdog. halt instruction if the watchdog reset on halt option is selected by option byte, a halt instruction causes an im- mediate reset generation if the watchdog is acti- vated (wdga bit is set). 11.1.6.1 using halt mode with the wdg (option) if the watchdog reset on halt option is not se- lected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt in struction stops the oscilla- tor. when the os cillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external inter- rupt or a reset. if an external interrupt is received, the wdg re- starts counting after 4096 cpu clocks. if a reset is generated, the wdg is disabled (reset state). recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. ? for the same reason, re initialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. ? as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 11.1.7 interrupts none. cr register initial value wdg timeout period (ms) max ffh 393.216 min c0h 6.144 ST7260 38/117 watchdog timer (cont?d) 11.1.8 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 16. watchdog timer register map and reset values 70 wdga t6 t5 t4 t3 t2 t1 t0 address (hex.) register label 76543210 0ch wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 ST7260 39/117 11.2 16-bit timer 11.2.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few micros econds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 11.2.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least four times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 24 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be ?1?. 11.2.3 functional description 11.2.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter register (cr): ? counter high register (chr) is the most sig- nificant byte (ms byte). ? counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) ? alternate counter high register (achr) is the m ost significant byte (ms byte). ? alternate counter low r egister (aclr) is the least significant byte (ls byte ). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register , as illustrated in table 17, "clock control bits" . the value in the counter reg- ister repeats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. ST7260 40/117 16-bit timer (cont?d) figure 24. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr ST7260 41/117 16-bit timer (cont?d) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value rema ins unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: ? the tof bit of the sr register is set. ? a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cl eared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 11.2.3.2 external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchron ized with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + ? t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte ST7260 42/117 16-bit timer (cont?d) figure 25. counter timing diagram, internal clock divided by 2 figure 26. counter timing diagram, internal clock divided by 4 figure 27. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 ST7260 43/117 16-bit timer (cont?d) 11.2.3.3 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected on the icap i pin (see figure 28 ). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function select the follow- ing in the cr2 register: ? select the timer clock (cc[1:0]) (see table 17, "clock control bits" ). ? select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: ? set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull- up without interrupt if this configuration is availa- ble). when an input capture occurs: ? icf i bit is set. ? the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 29 ). ? a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the two input capture functions can be used together even if the timer also uses the two out- put compare functions. 4. in one pulse mode and pwm mode only input capture 2 can be used. 5. the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icap i pins is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with interrupt genera- tion in order to measure events that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr ST7260 44/117 16-bit timer (cont?d) figure 28. input capture block diagram figure 29. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the active edge. ST7260 45/117 16-bit timer (cont?d) 11.2.3.4 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16- bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: ? assigns pins with a prog rammable value if the oc i e bit is set ? sets a flag in the status register ? generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: ? set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. ? select the timer clock (cc[1:0]) (see table 17, "clock control bits" ). and select the following in the cr1 register: ? select the olvl i bit to applied to the ocmp i pins after the match occurs. ? set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ? ocf i bit is set. ? the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). ? a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 17, "clock control bits" ) if the timer clock is an external clock, the formula is: where: ? t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: ? write to the oc i hr register (further compares are inhibited). ? read the sr register (first step of the clearance of the ocf i bit, which may be already set). ? write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr ? oc i r = ? t * f cpu presc ? oc i r = ? t * f ext ST7260 46/117 16-bit timer (cont?d) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 31 on page 47 ). this behavior is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value (see figure 32 on page 47 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. figure 30. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 ST7260 47/117 16-bit timer (cont?d) figure 31. output compare timing diagram, f timer =f cpu /2 figure 32. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) ST7260 48/117 16-bit timer (cont?d) 11.2.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 17, "clock control bits" ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffc h and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the val- ue fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 17, "clock control bits" ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 33 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1 = olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level olvl2 is dedi- cated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 ST7260 49/117 16-bit timer (cont?d) figure 33. one pulse mode timing example figure 34. pulse width modulation mode timi ng example with 2 output compare functions note: on timers with only one output compare register, a fixed frequency pwm signal can be generated using the output compare and the counter overflow to define the pulse length. counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 fffc fffd fffe 2ed0 2ed1 2ed2 ST7260 50/117 16-bit timer (cont?d) 11.2.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r regis- ter, and so this functionality can not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values writ- ten in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 17, "clock control bits" ). if olvl1 = 1 and olvl2 = 0 the length of the pos- itive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a cont inuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 17, "clock control bits" ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 34 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 ST7260 51/117 16-bit timer (cont?d) 11.2.4 low power modes 11.2.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 11.2.6 summary of timer modes 1) see note 4 in section 11.2.3.5, "one pulse mode" 2) see note 5 in section 11.2.3.5, "one pulse mode" 3) see note 4 in section 11.2.3.6, "pulse width modulation mode" mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer regist ers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting re sumes from the previous count when the mcu is woken up by an interrupt with ?e xit from halt mode? capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detecti on circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt wi th ?exit from halt m ode? capability, the icf i bit is set, and the counter value present when exiting fr om halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) one pulse mode no not recommended 1) no partially 2) pwm mode not recommended 3) no ST7260 52/117 16-bit timer (cont?d) 11.2.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no succes sful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge tr iggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 ST7260 53/117 16-bit timer (cont?d) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 17. clock control bits note : if the external clock pi n is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge tr iggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 1 f cpu / 8 1 0 external clock (where available) 1 ST7260 54/117 16-bit timer (cont?d) control/status register (csr) read/write (bits 7:3 read only) reset value: xxxx x0xx (xxh) bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disa- bled the output functions (ocmp1 and ocmp2 pins) to reduce power cons umption. access to the timer registers is still ava ilable, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, mu st be kept cleared. 70 icf1 ocf1 tof icf2 ocf2 timd 0 0 ST7260 55/117 16-bit timer (cont?d) input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb ST7260 56/117 16-bit timer (cont?d) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb ST7260 57/117 16-bit timer (cont?d) table 18. 16-bit timer register map and reset values address (hex.) register label 76543210 11 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 12 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 13 csr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 timd 0 0 0 0 0 14 ic1hr reset value msb lsb 15 ic1lr reset value msb lsb 16 oc1hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 17 oc1lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 18 chr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 1 lsb 1 19 clr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 0 lsb 0 1a achr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 1 lsb 1 1b aclr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 0 lsb 0 1c ic2hr reset value msb lsb 1d ic2lr reset value msb lsb 1e oc2hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 1f oc2lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 ST7260 58/117 11.3 serial communications interface (sci) 11.3.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 11.3.2 main features full duplex, asynchronous communications nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 250k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver four error detection flags: ? overrun error ? noise error ? frame error ? parity error six interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected ? parity error parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 11.3.3 general description the interface is externally connected to another device by two pins (see figure 36 ): ? tdo: transmit data output. when the transmit- ter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. ? rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: ? an idle line prior to transmission or reception ? a start bit ? a data word (8 or 9 bits) least significant bit first ? a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: ? a conventional type for commonly-used baud rates. ST7260 59/117 serial communications interface (cont?d) figure 35. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 baud rate generator sbk rwu re te ilie rie tcie tie cr2 ST7260 60/117 serial communications interface (cont?d) 11.3.4 functional description the block diagram of the serial control interface, is shown in figure 35 it contains 6 dedicated reg- isters: ? two control registers (scicr1 & scicr2) ? a status register (scisr) ? a baud rate register (scibrr) refer to the register descriptions in section 11.3.7 for the definitions of each bit. 11.3.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 35 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 36. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame ST7260 61/117 serial communications interface (cont?d) 11.3.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 35 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 36 ). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. ST7260 62/117 serial communications interface (cont?d) 11.3.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 35 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the rdr register as long as the rdrf bit is not cleared. when a overrun error occurs: ? the or bit is set. ? the rdr content will not be lost. ? the shift register will be overwritten. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge de- tection as well as three valid samples. when noise is detected in a frame: ? the nf flag is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read op- eration followed by a scidr register read opera- tion. during reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this frame and the nf flag is set internally (not accessible to the user). this nf flag is accessible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the applica- tion software when the first valid byte is received. see also section 11.3.4.9 . ST7260 63/117 serial communications interface (cont?d) framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. 11.3.4.4 baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 11.3.4.5 receiver muting and wake-up feature in multiprocessor configurat ions it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interr upts are inhibited. a muted receiver may be awakened by one of the following two ways: ? by idle line detection if the wake bit is reset, ? by address mark detectio n if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution : in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu=1) and a address mark wake up event occurs (rwu is reset) before the write operation, the rwu bit will be set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu ST7260 64/117 serial communications interface (cont?d) 11.3.4.6 parity control parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in table 19 . table 19. frame formats legend: sb = start bit, stb = stop bit, pb = parity bit note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of ?1s? if even parity is selected (ps=0) or an odd number of ?1s? if odd parity is se- lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen- erated if pie is set in the scicr1 register. 11.3.4.7 sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detec- tion, all the three samples should have the same value otherwise the noise flag (nf) is set. for ex- ample: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be ?1?, but the noise flag bit is be set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the de- sired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal sampling clock of the microcon- troller samples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32s & 36s respectively (the first sample starting ideally at 0s). but if the falling edge of the internal clock oc- curs just before the pin value changes, the sam- ples would then be out of sync by ~4us. this means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchroniza- tion with the internal sampling clock). m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | ST7260 65/117 serial communications interface (cont?d) 11.3.4.8 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error (local oscillator error of the tr ansmitter or the trans- mitter is transmitting at a different baud rate). ?d quant : error due to the baud rate quantisa- tion of the receiver. ?d rec : deviation of the lo cal oscillator of the receiver: this deviation can occur during the reception of one complete sci message as- suming that the deviation has been compen- sated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% 11.3.4.9 noise error causes see also description of noise error in section 11.3.4.3 . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not detected. a falling edge is considered to be valid if the 3 consecu- tive samples before t he falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit re- ception if the following condition occurs: ? during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag getting set. figure 37. bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 ST7260 66/117 serial communications interface (cont?d) 11.3.5 low power modes 11.3.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corre- sponding enable control bi t is set and the inter- rupt mask in the cc regist er is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmit- ting/receiving until halt mode is exit- ed. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com- plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error detected or yes no idle line detected idle ilie yes no parity error pe pie yes no ST7260 67/117 serial communications interface (cont?d) 11.3.7 register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol- lowed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data will not be transfer red to the shift reg- ister unless the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardwar e when transmission of a frame containing data is complete. an interrupt is generated if tcie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre- amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift re gister will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be tr ansferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a parity error oc- curs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inter- rupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error 70 tdre tc rdrf idle or nf fe pe ST7260 68/117 serial communications interface (cont?d) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (gener- ation and detection). when the parity control is en- abled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmis- sion). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected afte r the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled. 70 r8 t8 scid m wake pce ps pie ST7260 69/117 serial communications interface (cont?d) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: ? during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. ? when te is set there is a 1 bit-time delay before the transmission starts. caution: the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set). bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it cannot function in mute mode with wakeup by idle line detection. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter will send a break word at the end of the current word. 70 tie tcie rie ilie te re rwu sbk ST7260 70/117 serial communications interface (cont?d) data register (scidr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 35 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 35 ). baud rate register (scibrr) read/write reset value: 0000 0000 (00h) bits 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate clock. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 pr prescaling factor scp1 scp0 ST7260 71/117 table 20. sci register map and reset values address (hex.) register label 76543210 20 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 21 scidr reset value dr7 x dr6 x dr5 x dr4 x dr3 x dr2 x dr1 x dr0 x 22 scibrr reset value scp1 0 scp0 0 sct2 x sct1 x sct0 x scr2 x scr1 x scr0 x 23 scicr1 reset value r8 x t8 x scid 0 m x wake x pce 0 ps 0 pie 0 24 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 ST7260 72/117 11.4 usb interface (usb) 11.4.1 introduction the usb interface implements a low-speed func- tion interface between the usb and the st7 mi- crocontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and dma. no external components are needed apart from the external pull-up on usbdm for low speed recognition by the usb host. the use of dma architecture allows the endpoint definition to be completely flexible. endpoints can be config- ured by software as in or out. 11.4.2 main features usb specification version 1.1 compliant supports low-speed usb protocol two or three endpoints (including default one) depending on the device (see device feature list and register map) crc generation/checking, nrzi encoding/ decoding and bit-stuffing usb suspend/resume operations dma data transfers on-chip 3.3v regulator on-chip usb transceiver 11.4.3 functional description the block diagram in figure 38 , gives an overview of the usb interface hardware. for general information on the usb, refer to the ?universal serial bus specifications? document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmis- sion/reception, and handshaking as required by the usb standard. it also performs frame format- ting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. dma when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place, using dma. at the end of the transaction, an interrupt is generated. interrupts by reading the interrupt status register, applica- tion software can know which usb event has oc- curred. figure 38. usb block diagram cpu memory transceiver 3.3v voltage regulator sie endpoint dma interrupt address, and interrupts usbdm usbdp usbvcc 6 mhz registers registers data buses usbgnd ST7260 73/117 usb interface (cont?d) 11.4.4 register description dma address register (dmar) read / write reset value: undefined bits 7:0= da[15:8] dma address bits 15-8. software must write the start address of the dma memory area whose most significant bits are given by da15-da6. the remaining 6 address bits are set by hardware. see the description of the idr register and figure 39 . interrupt/dma register (idr) read / write reset value: xxxx 0000 (x0h) bits 7:6 = da[7:6] dma address bits 7-6. software must reset these bits. see the descrip- tion of the dmar register and figure 39 . bits 5:4 = ep[1:0] endpoint number (read-only). these bits identify the endpoint which required at- tention. 00: endpoint 0 01: endpoint 1 10: endpoint 2 when a ctr interrupt occurs (see register istr) the software should read the ep bits to identify the endpoint which has sent or received a packet. bits 3:0 = cnt[3:0] byte count (read only). this field shows how many data bytes have been received during the last data reception. note: not valid for data transmission. figure 39. dma buffers 70 da15 da14 da13 da12 da11 da10 da9 da8 70 da7 da6 ep1 ep0 cnt3 cnt2 cnt1 cnt0 endpoint 0 rx endpoint 0 tx endpoint 2 rx endpoint 1 tx 000000 000111 001000 001111 010000 010111 011000 011111 da15-6,000000 endpoint 1 rx endpoint 2 tx 100000 100111 101000 101111 ST7260 74/117 usb interface (cont?d) pid register (pidr) read only reset value: xx00 0000 (x0h) bits 7:6 = tp[3:2] token pid bits 3 & 2 . usb token pids are encoded in four bits. tp[3:2] correspond to the variable token pid bits 3 & 2. note: pid bits 1 & 0 have a fixed value of 01. when a ctr interrupt occurs (see register istr) the software should read the tp3 and tp2 bits to retrieve the pid name of the token received. the usb standard defines tp bits as: bits 5:3 reserved. forced by hardware to 0. bit 2 = rx_sez received single-ended zero this bit indicates the status of the rx_sez trans- ceiver output. 0: no se0 (single-ended zero) state 1: usb lines are in se0 (single-ended zero) state bit 1 = rxd received data 0: no k-state 1: usb lines are in k-state this bit indicates the status of the rxd transceiver output (differential receiver output). note: if the environment is noisy, the rx_sez and rxd bits can be used to secure the application. by interpreting the status, software can distinguish a valid end suspend event from a spurious wake-up due to noise on the external usb line. a valid end suspend is followed by a resume or reset se- quence. a resume is indicated by rxd=1, a re- set is indicated by rx_sez=1. bit 0 = reserved. forced by hardware to 0. interrupt status register (istr) read / write reset value: 0000 0000 (00h) when an interrupt occurs these bits are set by hardware. software must read them to determine the interrupt type and clear them after servicing. note: these bits cannot be set by software. bit 7 = susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb bus. the suspend request check is active immedi- ately after each usb reset event and its disabled by hardware when suspend mode is forced (fsusp bit of ctlr register) until the end of resume sequence. bit 6 = dovr dma over/underrun . this bit is set by hardware if the st7 processor can?t answer a dma request in time. 0: no over/underrun detected 1: over/underrun detected bit 5 = ctr correct transfer. this bit is set by hardware when a correct transfer operation is per- formed. the type of transfer can be determined by looking at bits tp3-tp2 in register pidr. the end- point on which the transfer was made is identified by bits ep1-ep0 in register idr. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack handshakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. bit 4 = err error. this bit is set by hardware whenever one of the er- rors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing or nonstandard framing error detected 70 tp3 tp2 0 0 0 rx_ sez rxd 0 tp3 tp2 pid name 00 out 10 in 11 setup 70 susp dovr ctr err iovr esusp reset sof ST7260 75/117 usb interface (cont?d) bit 3 = iovr interrupt overrun. this bit is set when hardware tries to set err, or sof before they have been cleared by software. 0: no overrun detected 1: overrun detected bit 2 = esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb in- terface up from suspend mode. this interrupt is serviced by a specific vector, in or- der to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected bit 1 = reset usb reset. this bit is set by hardware when the usb reset se- quence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0ra, ep0rb, ep1ra, ep1rb, ep2ra and ep2rb registers are reset by a usb reset. bit 0 = sof start of frame. this bit is set by hardwa re when a low-speed sof indication (keep-alive strobe) is seen on the usb bus. it is also issued at the end of a resume se- quence. 0: no sof signal detected 1: sof signal detected note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruc- tion where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read- modify-write instructions like and , xor.. interrupt mask register (imr) read / write reset value: 0000 0000 (00h) bits 7:0 = these bits are mask bits for all interrupt condition bits included in the istr. whenever one of the imr bits is set, if the corresponding istr bit is set, and the i bit in the cc register is cleared, an interrupt request is generated. for an explanation of each bit, please refer to the corresponding bit description in istr. control register (ctlr) read / write reset value: 0000 0110 (06h) bits 7:4 = reserved. forced by hardware to 0. bit 3 = resume resume . this bit is set by software to wake-up the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. bit 2 = pdwn power down . this bit is set by software to turn off the 3.3v on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, soft- ware should allow at least 3 s for stabilisation of the power supply before using the usb interface. bit 1 = fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be halted allowing at least 600 ns before issuing the halt instruction. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it resets this bit (it can also be reset by software). bit 0 = fres force reset. this bit is set by software to force a reset of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb is held in reset state until software clears this bit, at whic h point a ?usb-reset? in- terrupt will be gen erated if enabled. 70 sus pm dov rm ctr m err m iovr m esu spm res etm sof m 70 0 0 0 0 resume pdwn fsusp fres ST7260 76/117 usb interface (cont?d) device address register (daddr) read / write reset value: 0000 0000 (00h) bit 7 = reserved. forced by hardware to 0. bits 6:0 = add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received from the usb bus or forced through bit fres in the ctlr register. endpoint n register a (epnra) read / write reset value: 0000 xxxx (0xh) these registers ( ep0ra , ep1ra and ep2ra ) are used for controlling data transmission. they are also reset by the usb bus reset. note : endpoint 2 and the ep2ra register are not available on some devices (see device feature list and register map). bit 7 = st_out status out. this bit is set by software to indicate that a status out packet is expected: in this case, all nonzero out data transfers on the endpoint are stalled instead of being acked. when st_out is reset, out transactions can have any number of bytes, as needed. bit 6 = dtog_tx data toggle, for transmission transfers. it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware at the re- ception of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dtog_rx (see epnrb) are normally updated by hardware, at the receipt of a relevant pid. they can be also written by software. bits 5:4 = stat_tx[1:0] status bits, for transmis- sion transfers. these bits contain the information about the end- point status, whic h are listed below: these bits are written by software. hardware sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) related to a in or setup transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. bits 3:0 = tbc[3:0] transmit byte count for end- point n. before transmissi on, after filling the transmit buff- er, software must write in the tbc field the trans- mit packet size expressed in bytes (in the range 0- 8). warning: any value outside the range 0-8 will- induce undesired effects (such as continuous data transmission). 70 0 add6 add5 add4 add3 add2 add1 add0 70 st_ out dtog _tx stat _tx1 stat _tx0 tbc 3 tbc 2 tbc 1 tbc 0 stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission. ST7260 77/117 usb interface (cont?d) endpoint n register b (epnrb) read / write reset value: 0000 xxxx (0xh) these registers ( ep1rb and ep2rb ) are used for controlling data reception on endpoints 1 and 2. they are also reset by the usb bus reset. note : endpoint 2 and the ep2rb register are not available on some devices (see device feature list and register map). bit 7 = ctrl control. this bit should be 0. note: if this bit is 1, the endpoint is a control end- point. (endpoint 0 is always a control endpoint, but it is possible to have more than one control end- point). bit 6 = dtog_rx data toggle, for reception trans- fers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by ha rdware in the first stage (setup stage) of a control transfer (setup trans- actions start always with data0 pid). the receiv- er toggles dtog_rx only if it receives a correct data packet and the packet?s data pid matches the receiver sequence bit. bits 5:4 = stat_rx [1:0] status bits, for reception transfers. these bits contain the information about the end- point status, which are listed below: these bits are written by software. hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) related to an out or set- up transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. bits 3:0 = ea[3:0] endpoint address . software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. usually ep1rb contains ?0001? and ep2rb contains ?0010?. endpoint 0 register b (ep0rb) read / write reset value: 1000 0000 (80h) this register is used fo r controlling data reception on endpoint 0. it is also reset by the usb bus re- set. bit 7 = forced by hardware to 1. bits 6:4 = refer to the epnrb register for a de- scription of these bits. bits 3:0 = forced by hardware to 0. 70 ctrl dtog _rx stat _rx1 stat _rx0 ea3 ea2 ea1 ea0 stat_rx1 stat_rx0 meaning 00 disabled : reception transfers cannot be exe- cuted. 01 stall: the endpoint is stalled and all reception requests result in a stall handshake. 10 nak : the endpoint is na- ked and all reception re- quests result in a nak handshake. 11 valid : this endpoint is enabled for reception. 70 1 dtog rx stat rx1 stat rx0 0000 stat_rx1 stat_rx0 meaning ST7260 78/117 usb interface (cont?d) 11.4.5 programming considerations the interaction between the usb interface and the application program is described below. apart from system reset, action is always initiated by the usb interface, driven by one of the usb events associated with the interrupt status register (is- tr) bits. 11.4.5.1 initializing the registers at system reset, the softwa re must initialize all reg- isters to enable the usb interface to properly gen- erate interrupts and dma requests. 1. initialize the dmar, idr, and imr registers (choice of enabled interrupts, address of dma buffers). refer the parag raph titled initializing the dma buffers. 2. initialize the ep0ra and ep0rb registers to enable accesses to address 0 and endpoint 0 to support usb enumeration. refer to the para- graph titled endpoint initialization. 3. when addresses are received through this channel, update the content of the daddr. 4. if needed, write the endpoint numbers in the ea fields in the ep1rb and ep2rb register. 11.4.5.2 initializing dma buffers the dma buffers are a contiguous zone of memo- ry whose maximum size is 48 bytes. they can be placed anywhere in the memory space to enable the reception of messages. the 10 most signifi- cant bits of the start of this memory area are spec- ified by bits da15-da6 in registers dmar and idr, the remaining bits are 0. the memory map is shown in figure 39 . each buffer is filled starting from the bottom (last 3 address bits=000) up. 11.4.5.3 endpoint initialization to be ready to receive: set stat_rx to valid (11b) in ep0rb to enable reception. to be ready to transmit: 1. write the data in the dma transmit buffer. 2. in register epnra, specify the number of bytes to be transmitted in the tbc field 3. enable the endpoint by setting the stat_tx bits to valid (11b) in epnra. note: once transmission and/or reception are en- abled, registers epnra and/or epnrb (respec- tively) must not be modified by software, as the hardware can change their value on the fly. when the operation is completed, they can be ac- cessed again to enable a new operation. 11.4.5.4 interrupt handling start of frame (sof) the interrupt service routine may monitor the sof events for a 1 ms synchronization event to the usb bus. this interrupt is generated at the end of a resume sequence and can also be used to de- tect this event. usb reset (reset) when this event occurs, the daddr register is re- set, and communication is disabled in all endpoint registers (the usb interfac e will not resp ond to any packet). software is re sponsible for reenabling endpoint 0 within 10 ms of the end of reset. to do this, set the stat_rx bits in the ep0rb register to valid. suspend (susp) the cpu is warned about the lack of bus activity for more than 3 ms, which is a suspend request. the software should set the usb interface to sus- pend mode and execute an st7 halt instruction to meet the usb-specified power constraints. end suspend (esusp) the cpu is alerted by activity on the usb, which causes an esusp interrupt. the st7 automatical- ly terminates halt mode. correct transfer (ctr) 1. when this event occurs, the hardware automat- ically sets the stat_tx or stat_rx to nak. note: every valid endpoint is naked until soft- ware clears the ctr bit in the istr register, independently of the endpoint number addressed by the transfer which generated the ctr interrupt. note: if the event triggering the ctr interrupt is a setup transaction, both stat_tx and stat_rx are set to nak. 2. read the pidr to obtain the token and the idr to get the endpoint number related to the last transfer. note: when a ctr interrupt occurs, the tp3- tp2 bits in the pidr register and ep1-ep0 bits in the idr register stay unchanged until the ctr bit in the istr register is cleared. 3. clear the ctr bit in the istr register. ST7260 79/117 usb interface (cont?d) table 21. usb register map and reset values address (hex.) register name 7 6 5 4 3210 25 pidr reset value tp3 x tp2 x 0 0 0 0 0 0 rx_sez 0 rxd 0 0 0 26 dmar reset value da15 x da14 x da13 x da12 x da11 x da10 x da9 x da8 x 27 idr reset value da7 x da6 x ep1 x ep0 x cnt3 0 cnt2 0 cnt1 0 cnt0 0 28 istr reset value susp 0 dovr 0 ctr 0 err 0 iovr 0 esusp 0 reset 0 sof 0 29 imr reset value suspm 0 dovrm 0 ctrm 0 errm 0 iovrm 0 esuspm 0 resetm 0 sofm 0 2a ctlr reset value 0 0 0 0 0 0 0 0 resume 0 pdwn 1 fsusp 1 fres 0 2b daddr reset value 0 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 2c ep0ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2d ep0rb reset value 1 1 dtog_rx 0 stat_rx1 0 stat_rx0 0 0 0 0 0 0 0 0 0 2e ep1ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2f ep1rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x 30 ep2ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 31 ep2rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x ST7260 80/117 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 22. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10. w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10] ,#7,skip 00..ff 00..ff byte + 3 ST7260 81/117 st7 addressing modes (cont?d) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, t hus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations ST7260 82/117 st7 addressing modes (cont?d) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 23. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative ST7260 83/117 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf ST7260 84/117 instruction groups (cont?d) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine retu rn pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > ST7260 85/117 instruction groups (cont?d) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z ST7260 86/117 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v. they are given only as de- sign guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 40 . figure 40. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 41 . figure 41. pin input voltage c l st7 pin v in st7 pin ST7260 87/117 13.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an uni ntentional internal reset is generated or an unexpected change of the i/o configuration occurs (for exampl e, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in ST7260 89/117 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). notes: 1. oscillator and watchdog running. all others peripherals disabled. 2. usb transceiver is powered down. 3. not tested in production, guaranteed by characterization. 4. cpu in halt mode. current consumption of exter nal pull-up (1.5kohms to usbvcc) and pull-down (15kohms to v ssa ) not included. figure 43. typ. i dd in run at 4 and 8 mhz f cpu figure 44. typ. i dd in wait at 4 and 8 mhz f cpu symbol parameter conditions typ max unit ? i dd( ? ta) supply current variation vs. temperature constant v dd and f cpu 10 3) % i dd cpu run mode i/os in input mode f cpu = 4 mhz 7.5 9 1)3) ma f cpu = 8 mhz 10.5 13 1) cpu wait mode f cpu = 4 mhz 6 8 3) ma f cpu = 8 mhz 8.5 11 1) cpu halt mode 2) lvd disabled 25 40 3) a usb suspend mode 4) lvd disabled 100 120 a lvd enabled 230 idd run (ma) at fcpu=4 and 8mhz 0 2 4 6 8 10 12 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) idd run (ma) 8mhz 4mhz idd wfi (ma) at fcpu=4 and 8mhz 0 2 4 6 8 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) idd wfi (ma) 8mhz 4mhz ST7260 90/117 13.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 13.5.1 general timings notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instru ction execution. 13.5.2 control timing characteristics note: 1. not tested in production, guaranteed by characterization. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time f cpu =8mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = ? t c(inst) + 10 t cpu f cpu =8mhz 10 22 t cpu 1.25 2.75 s control timings symbol parameter conditions value unit min typ. max f osc oscillator frequency 24 mhz f cpu operating frequency 8 mhz t rl external reset input pulse width 2520 ns t porl internal power reset duration 4096 t cpu t dogl watchdog or low voltage reset output pulse width 200 300 ns t dog watchdog time-out f cpu = 8mhz 49152 6.144 3145728 393.216 t cpu ms t oxov crystal oscillator start-up time 20 1) 30 40 1) ms t ddr power up rise time from v dd = 0 to 4v 100 1) ms ST7260 91/117 clock and timing characteristics (cont?d) 13.5.3 external clock source note: 1. data based on design simulation and/or technology characteristics, no t tested in production. figure 45. typical application with an external clock source figure 46. typical application with a crystal resonator symbol parameter conditions min typ max unit v oscinh oscin input pin high level voltage see figure 45 0.7xv dd v dd v v oscinl oscin input pin low level voltage v ss 0.3xv dd t w(oscinh) t w(oscinl) oscin high or low time 1) 15 ns t r(oscin) t f(oscin) oscin rise or fall time 1) 15 i l oscx input leakage current v ss v in v dd 1 a oscin oscout f osc external st72xxx clock source not connected internally v oscinl v oscinh t r(oscin) t f(oscin) t w(oscinh) t w(oscinl) i l 90% 10% oscout oscin f osc c l1 c l2 i 2 r f st72xxx resonator ST7260 92/117 13.6 memory characteristics subject to general operating conditions for f cpu , and t a unless otherwise specified. 13.6.1 ram and hardware registers note: 1. guaranteed by design. not tested in production. 13.6.2 flash memory operating conditions: f cpu = 8 mhz. note: 1. refer to the flash programming reference manual for the typical hdflash programming and erase timing values. figure 47. two typical applications with v pp pin 1) note: 1. when the icp mode is not required by the application, v pp pin must be tied to v ss . symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 2.0 v dual voltage flash memory 1) symbol parameter conditions min typ max unit f cpu operating frequency read mode 8 mhz write / erase mode, t a =25c 8 v pp programming voltage 4.0v v dd 5.5v 11.4 12.6 v i pp v pp current write / erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a 55c 40 years n rw write erase cycles t a =25c 100 cycles v pp st72xxx 10k ? programming tool v pp st72xxx ST7260 93/117 13.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 13.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. note: 1. data based on characterization results, not tested in production. symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8 mhz, conforms to iec 1000-4-2 4b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8 mhz, conforms to iec 1000-4-4 4a symbol parameter conditions monitored frequency band max vs. [f osc / f cpu ] unit 16/8 mhz s emi peak level 1) v dd = 5v, t a = +25c, conforming to sae j 1752/3 note: refer to application note an1709 for data on other package types. 0.1mhz to 30mhz 36 db v 30mhz to 130mhz 39 130mhz to 1ghz 26 sae emi level 3.5 - ST7260 94/117 emc characteristics (cont?d) 13.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measuremen t methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to the application note an1181. 13.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22- a114a/a115a standard. absolute maximum ratings note: 1. data based on characterization results, not tested in production. 13.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1 000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities note: 1. class description: a class is an stmicr oelectronics internal specif ication. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standar d. b class strictly covers all the jedec criteria (int ernational standard). symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a ST7260 95/117 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. configuration not recommended, all unused pins must be kept at a fixed voltage: using t he output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 48 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristic s, not tested in production. this value depends on v dd and tem- perature values. 2. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 49 ). 3. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. figure 48. two typical applications with unused i/o pin figure 49. typ. i pu vs. v dd symbol parameter conditions min typ max unit v il input low level voltage 0.3xv dd v v ih input high level voltage 0.7xv dd v in input voltage true open drain i/o pins v ss 6.0 v other i/o pins v dd v hys schmitt trigger voltage hysteresis 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption induced by each floating input pin 1) floating input mode 400 r pu weak pull-up equivalent resistor 2) v in = v ss v dd =5 v 50 90 120 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time c l =50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 25 t w(it)in external interrupt pulse time 3) 1t cpu 10k ? unused i/o port st72xxx 10k ? unused i/o port st72xxx v dd pull-up current (a) 0 10 20 30 40 50 60 70 80 90 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) pull-up current (a) ST7260 96/117 figure 50. typ. r pu vs. v dd 13.8.2 output driving current subject to general operating condition for v dd , f cpu , and t a unless otherwise specified. notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2 and the sum of i io (i/ o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vdd . true open drain i/o pins does not have v oh . figure 51. v ol standard v dd =5 v figure 52. v ol high sink v dd =5 v rpu (kohm) 0 20 40 60 80 100 120 140 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) rpu (kohm) symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when up to 8 pins are sunk at the same time, port a0, port a(3:7), port c(0:2) v dd =5 v i io =+1.6 ma 0.4 v output low level voltage for a high sink i/o pin when up to 4 pins are sunk at the same time, port b(0:7) i io =+10 ma 1.3 output low level voltage for a very high sink i/o pin when up to 2 pins are sunk at the same time, port a1, port a2 i io =+25 ma 1.5 v oh 2) output high level voltage for an i/o pin when up to 8 pins are sourced at same time i io =-10 ma v dd -1.3 i io =-1.6 ma v dd -0.8 vol_2ma (mv) at vdd=5v 0 50 100 150 200 250 11.522.533.54 iio (ma) vol_2ma (mv) vol_10ma (v) at vdd=5v 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 5 7 9 11 13 15 17 19 iio (ma) vol_10ma (v) ST7260 97/117 figure 53. v ol very high sink v dd =5 v figure 54. v ol standard vs. v dd figure 55. v ol high sink vs. v dd figure 56. v ol very high sink vs. v dd figure 57. |v dd -v oh | @ v dd =5 v (low current) figure 58. |v dd -v oh | @ v dd =5 v (high current) vol_25ma (v) at vdd=5v 0.35 0.45 0.55 0.65 0.75 0.85 0.95 15 20 25 30 35 iio (ma) vol_25ma (v) vol_2ma (mv) at iio=2ma 105 110 115 120 125 130 44.24.44.64.855.25.4 vdd (v) vol_2ma (mv) vol_10ma (v) at iio=10ma 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) vol_10ma (v) vol_25ma (v) at iio=25ma 0.6 0.65 0.7 0.75 0.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) vol_25ma (v) |vdd - voh| (v) at vdd=5v 0 0.05 0.1 0.15 0.2 0.25 0.3 1 1.5 2 2.5 3 3.5 4 -iio (ma) |vdd - voh| (v) |vdd - voh| (v) at vdd=5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2 7 12 17 -iio (ma) |vdd - voh| (v) ST7260 98/117 figure 59. |v dd -v oh | @ i io =2 ma (low current) figure 60. |v dd -v oh | @ i io =10ma (high current) |vdd - voh| (v) at iio=-2ma 0.12 0.125 0.13 0.135 0.14 0.145 0.15 0.155 0.16 0.165 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) |vdd - voh| (v) |vdd - voh| (v) at iio=-10ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) |vdd - voh| (v) ST7260 99/117 13.9 control pin characteristics 13.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. hysteresis voltage between schmitt tr igger switching levels. based on c haracterization results, not tested. 2. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2 and the sum of i io (i/ o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resistive trans istor. this data is based on characterization results, not tested in production. 4. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. symbol parameter conditions min typ max unit v ih input high level voltage 0.7xv dd v dd v v il input low voltage v ss 0.3xv dd v v hys schmitt trigger voltage hysteresis 1) 400 mv v ol output low level voltage 2) v dd =5v i io =5 ma 0.8 v i io =7.5 ma 1.3 r on weak pull-up equivalent resistor 3) v in = v ss v dd =5 v 50 80 100 k ? t w(rstl)out generated reset pulse duration external pin or internal reset sources 6 30 1/f sfosc s t h(rstl)in external reset pulse hold time 4) 5 s ST7260 100/117 control pin characteristics (cont?d) figure 61. reset pin protection when lvd is enabled. 1)2)3)4) figure 62. reset pin protection when lvd is disabled. 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 99 . otherwise the reset will not be taken into account internally. ? because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must en- sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 13.2.2 on page 87 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: in case a capacitive power supply is used, it is recommended to connect a 1 m ? pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to i ccclk and reset circuit have been applied (see notes above). ? 2. check that the power supply is properly decoupled (100 nf + 10 f cl ose to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100 nf + 1m ? pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the power supply are key to avoi d any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10 nf pull-down on the reset pin with a 5 f to 20 f capacitor.? 0.01 f st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset reset external required 1 m ? optional (note 6) 0.0 1 f 0.01 f v dd external reset circuit user v dd 4.7 k ? required recommended for emc st72xxx pulse generator filter r on v dd watchdog internal reset ST7260 101/117 13.10 communication interface characteristics 13.10.1 usb - universal bus interface (operating conditions t a = 0 to +70c, v dd = 4.0 to 5.25v unless otherwise specified) notes: 1. rl is the load connected on the usb drivers. 2. all the voltages are measured from the local ground potential. 3. to improve emc performance (noise immunity), it is recommended to connect a 100nf capacitor to the usbvcc pin. figure 63. usb: data signal rise and fall time table 24. usb: low-speed electrical characteristics note: 1. for more detailed information, please refer to chapter 7 (electrical) of the usb specification (version 1.1). usb dc electrical characteristics symbol parameter conditions min. max. unit vdi differential input s ensitivity i(d+, d-) 0.2 v 2) vcm differential common mode range includes vdi range 0.8 2.5 vse single ended receiver threshold 0.8 2.0 vol static output low rl 1) of 1.5 kohms to 3.6v 0.3 voh static output high rl 1) of 15 kohms to v ss 2.8 3.6 usbv usbvcc: voltage level 3) v dd =5 v 3.00 3.60 differential data lines v ss tf tr crossover points vcrs symbol parameter conditions min max unit driver characteristics: tr rise time cl=50 pf 1) 75 ns cl=600 pf 1) 300 ns tf fall time cl=50 pf 1) 75 ns cl=600 pf 1) 300 ns trfm rise/ fall time matching tr/tf 80 120 % vcrs output signal crossover voltage 1.3 2.0 v ST7260 102/117 communication interface characteristics (cont?d) 13.10.2 sci - serial communications interface subject to general operating condition for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (rdi and tdo). symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8 mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ST7260 103/117 14 package characteristics in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level in- terconnect. the category of second level inter- connect is marked on the package and on the in- ner box label, in comp liance with jedec standard jesd97. the maximum ratings related to solder- ing conditions are also marked on the inner box la- bel. ecopack is an st tra demark. ecopack speci- fications are available at: www.st.com 14.1 package mechanical data figure 64. 24-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 15.20 15.60 0.599 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 24 c h x 45 l a a a1 e b d h e ST7260 104/117 figure 65. 40-lead very thin fine pitch quad flat no-lead package dim. mm inches 1) min typ max min typ max a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0.02 0.05 0.001 0.002 a2 0.65 1.00 0.026 0.039 a3 0.20 0.008 b 0.18 0.25 0.30 0.007 0.010 0.012 d 5.85 6.00 6.15 0.230 0.236 0.242 d2 2.75 2.9 3.05 0.108 0.114 0.120 e 5.85 6 6.15 0.230 0.236 0.242 e2 2.75 2.9 3.05 0.108 0.114 0.120 e 0.50 0.020 l 0.30 0.40 0.50 0.012 0.016 0.020 number of pins n 40 note 1. values in inches are converted from mm and rounded to 3 decimal digits. seating plane a d2 1 2 pin #1 id type c radius d e a1 a3 a2 b e e2 l ST7260 105/117 14.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipati on determined by the user. 2. the average chip-junction temperatur e can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) so24 qfn40 70 34 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c ST7260 106/117 14.3 soldering and glueability information recommended soldering information given only as design guidelines in figure 66 and figure 67 . recommended glue for smd plastic packages dedicated to molding co mpound with silicone: heraeus: pd945, pd955 loctite: 3615, 3298 figure 66. recommended wave soldering profile (with 37% sn and 63% pb) figure 67. recommended reflow soldering oven profile (mid jedec) 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec ST7260 107/117 15 device configuration and ordering information each device is available for production in user pro- grammable versions (high density flash) as well as in factory coded versions (fastrom). st72p60 devices are factory advanced service technique rom (fastrom) versions: they are factory programmed flash devices. st72f60 flash devices ar e shipped to custom- ers with a default content (ffh). this implies that flash devices have to be con- figured by the customer using the option byte while the rom devices are factory-configured. 15.1 option byte the option byte allows the hardware configuration of the microcontroller to be selected. the option byte has no address in the memory map and can be accessed only in programming mode using a standard st7 programming tool. the default contents of the flash is fixed to f7h. this means that all the options have ?1? as their default value, except lvd. in rom devices, the option byte is fixed in hard- ware by the rom code. option byte opt 7:6 = reserved. opt 5 = wdgsw hardware or software watch- dog this option bit selects the watchdog type. 0: hardware enabled 1: software enabled opt 4 = wdhalt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt 3 = lvd low voltage detector selection this option bit selects the lvd. 0: lvd enabled 1: lvd disabled important note: on rom devices this option bit is forced by st to 0 (lvd always enabled): opt 2 = reserved. opt 1 = osc24/12 oscillator selection this option bit selects the clock divider used to drive the usb interface at 6mhz. 0: 24 mhz oscillator 1: 12 mhz oscillator opt 0 = fmp_r flash memory read-out protec- tion this option indicates if the user flash memory is protected against read-out. read-out protection, when selected, provides a protection against pro- gram memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected, causes the whole user memory to be erased first and the de- vice can be reprogrammed. refer to the st7 flash programming reference manual and section 4.3.1 on page 14 for more details. 0: read-out protection enabled 1: read-out protection disabled 70 -- -- wdg sw wd halt lvd -- osc 24/12 fmp_ r ST7260 108/117 15.2 device ordering informat ion and transfer of customer code customer code is made up of the fastrom con- tents and the list of the selected options (if any). the fastrom contents are to be sent on dis- kette, or by electronic means, with the hexadeci- mal file in .s19 format generated by the develop- ment tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. see page 110 . refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 25. supported part numbers note: 1. /xxx stands for the rom code name assigned by stmicroelectronics sales type 1) program memory (bytes) ram (bytes) package st72f60k2u1 8 k flash 384 qfn40 st72f60e2m1 384 so24 st72f60k1u1 4 k flash 384 qfn40 st72f60e1m1 384 so24 ST7260k2u1/xxx 8 k rom 384 qfn40 ST7260e2m1/xxx 384 so24 ST7260k1u1/xxx 4 k rom 384 qfn40 ST7260e1m1/xxx 384 so24 st72p60k2u1 8 k fastrom 384 qfn40 st72p60e2m1 384 so24 st72p60k1u1 4 k fastrom 384 qfn40 st72p60e1m1 384 so24 contact st sales office for product availability ST7260 109/117 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//www.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st see table 26 and table 27 for more details. table 26. stmicroelectronics tools features note : 1. in-circuit programming (icp) interface for flash devices. table 27. dedicated stmicroe lectronics development tools note : 1. add suffix /eu or /us for the power supply for your region. in-circuit emulation p rogramming capability 1) software included st7 emulator yes, powerful emulation features including trace/ logic analyzer no st7 cd rom with: ? st7 assembly toolchain ? stvd7 powerful source level debugger for win 3.1, win 9x and nt ? c compiler demo versions ? windows programming tools for win 3.1, win 9x and nt st7 programming board no yes (all packages) supported products evaluation board st7 emulator st7 programming board ST7260 st7mdtuls-eval st7mdtu3-emu3 st7mdtu3-epb 1) ST7260 110/117 ST7260 microcontroller option list (last update: oct 2006) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rom or fastrom code must be sent in .s19 format. hex extension cannot be processed. stmicroelectronics references: device type/memory size/package (check only one option): ----------------------------------------------------------------------------------------- rom device: | 4k | 8k | ----------------------------------------------------------------------------------------- so24: | [ ] ST7260e1m1 | [ ] ST7260e2m1 | qfn40: | [ ] ST7260k1u1 | [ ] ST7260k2u1 | ------------------------------------------------------------------------------------------ fastrom: | 4k | 8k | ------------------------------------------------------------------------------------------ so24: | [ ] st72p60e1m1 | [ ] st72p60e2m1 | qfn40: | [ ] st72p60k1u1 | [ ] st72p60k2u1 | ------------------------------------------------------------------------------------------ die form: | 4k | 8k | ------------------------------------------------------------------------------------------ 24-pin: | [ ] (as e1m1) | [ ] (as e2m1) | 40-pin: | [ ] (as k1u1) | [ ] (as k2u1) | conditioning (check only one option): packaged product | die product (rom only. dice tested at 25c only) ------------------------------------------------------------------------------------------------------------------------ [ ] tape & reel (so package only) | [ ] tape & reel [ ] tube | [ ] inked wafer | [ ] sawn wafer on sticky foil special marking ( rom only): [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _" authorized characters are letters, di gits, '.', '-', '/' and spaces only. for marking, one line is possible wi th a maximum of 13 characters. watchdog selection: [ ] software activation [ ] hardware activation halt when watchdog on: [ ] reset [ ] no reset lvd reset * [ ] disabled* [ ] enabled* * lvd is forced to 0 (lvd always enabled) on rom devices oscillator selection: [ ] 24 mhz. [ ] 12 mhz. readout protection: [ ] disabled [ ] enabled date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . please download the latest versi on of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list ST7260 111/117 15.4 st7 application notes table 28. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative in- put voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art ST7260 112/117 an1947 st7mc pmac sine wave motor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscilla- tor an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an1039 st7 math utility routines table 28. st7 application notes identification description ST7260 113/117 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma-delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 28. st7 application notes identification description ST7260 114/117 16 known limitations 16.1 pa2 limitation with ocmp1 enabled description this limitation affects only rev b flash devices (with internal sales type 72f60xxxxx$x7); it has been corrected in rev w flash devices (with inter- nal sales type 72f60xxxxx$x9). note: refer to figure 68 on page 115 when output compare 1 function (ocmp1) on pin pa6 is enabled by setting the oc1e bit in the tcr2 register, pin pa2 is also affected. in particular, the pa2 pin is forced to be floating even if port configuration (paddr+padr) has set it as output low. however, it can be still used as an input. 16.2 unexpected reset fetch if an interrupt request occu rs while a "pop cc" in- struction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a "pop cc" instruction must always be preceded by a "sim" instruction. 16.3 sci wrong break duration description a single break character is sent by setting and re- setting the sbk bit in the scicr2 register. in some cases, the break ch aracter may have a long- er duration than expected: - 20 bits instead of 10 bits if m=0 - 22 bits instead of 11 bits if m=1. in the same way, as long as the sbk bit is set, break characters are sent to the tdo pin. this may lead to generate one break more than expect- ed. occurrence the occurrence of the problem is random and pro- portional to the baudrate. with a transmit frequen- cy of 19200 baud (fcpu=8mhz and sci- brr=0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with the communication protocol in the application, soft- ware can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the applica- tion is not doing anything between the idle and the break. this can be ensured by temporarily disa- bling interrupts. the exact sequence is: - disable interrupts - reset and set te (idle request) - set and reset sbk (break request) - re-enable interrupts 16.4 usb behavior with lvd disabled on rom devices, if the lvd is disabled, the usb is disabled by hardware. so, the lvd is forced by st to 0 (lvd enabled). refer to the ST7260 option list for details. ST7260 115/117 figure 68. identifying silicon revision from device marking and box label stmicroelectronics bulk id marking trace code total qty type xxxxxxxxxxxx xxxxxxxxxx b xxxxxxxxx xx xx xx xxxxxxxxxxx $x7 st7xxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 1. identify the silicon revision letter from either the devi ce package or the box label. for example, ? b ?, etc. 2. if the revision letter is not pres ent, obtain the silicon revision by contacting your local st office with the trace code information printed on either the box label or the device package. device package example example box label the silicon revision can be identified either by rev letter or obtained via a trace code. follow the procedure below: silicon rev trace code silicon rev ST7260 116/117 17 revision history date revision main changes 13-feb-2006 1 initial release 02-nov-2006 2 added known limitations se ction (with new pa2 limitation) ST7260 117/117 notes: please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in mi litary, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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